Sai Kaushik S

Hardware Enthusiast

About Me

  • Hello! I’m Kaushik, a passionate software engineer and aspiring researcher with a keen interest in computer architecture and high-performance computing. Currently based in Bangalore, I hold a B.Tech and M.Tech in Computer Science and Engineering from IIITDM Kancheepuram, where I developed a strong foundation in software development and engineering principles.

  • With experience in .NET technologies, C#, WPF, MVC, ASP.NET, and more, I’ve had the opportunity to work on impactful projects at KLA as Software Intern and Associate Software Engineer.

  • Want to utilize my skills to achieve real world targets, pipelined withincreasing my knowledge in the topics.

  • Beyond coding, I’m also an avid writer, currently working on a sci-fi mystery novel that intertwines suspense with intricate storytelling. When I’m not programming or writing, I enjoy exploring new technologies, engaging in thoughtful discussions, and sharing my knowledge with others. Feel free to connect with me or explore my projects and insights throughout this site!



Resume

Curriculum Vita

Experience

July 2023 - August 2024

Associate Software Engineer

KLA - Tencor Software, Chennai

  • Acquired knowledge of semiconductor domain and its production cycle.
  • Resolved bugs and feature requests in a 3-tier application.
  • Executed performance and stress tests on Oracle DB CRUD using C++ libraries (Pro*C, Rogue Wave and OCCI).
  • Designed and implemented UI elements for the application using C# WPF.

Technologies: C++, C#, WPF, Oracle DB, Microsoft Azure, Docker, RHEL Servers, Git

January 2023 - June 2023

Software Intern

KLA - Tencor Software, Chennai

  • Worked on a desktop application that collects logs from the system based on user-specified inputs.
  • Redesigned a web application that generates the throughput report from user-uploaded logs.

Technologies: Python, PyQt6, Django, React, Java, Bootstrap

May 2022 - October 2022

Software Intern

KLA - Tencor Software, Chennai

  • Developed a web application that reduces the creation and deployment of VMs on VMWare servers.
  • Reduced the deployment time of the VMs by 12x from 2 hours to 10 minutes.

Technologies: .NET Core, Angular, VMWare vSphere

May 2021 - December 2021

Research Intern

Shakti Group, IIT Madras, Chennai

  • Worked on QSPI and SDIO modules of the in-bred microprocessor.

Technologies: BlueSpec SystemVerilog

Education

July 2018 - May 2023

B. Tech. and M. Tech.
Computer Science and Engineering specialization in System Design

Indian Institute of Information Technology, Design and Manufacturing, Kancheepuram
Chennai

CGPA: 8.79 / 10

July 2016 - April 2018

Class 12
Karnataka State Board

Vidya Vardhaka Sangha Sardar Patel Pre-University College
Bangalore

Percentage: 93.33%

July 2015 - May 2016

Class 10
CBSE Board

Narayana e-Techno School, Ramamurthy Nagar
Bangalore

CGPA: 10 / 10

Skills

Proficiency

Skills

Programming Languages


Software Tools


Frameworks

Languages

  • English (Full Professional Proficiency)
  • Hindi (Limited Working Proficiency)
  • Telugu (Native / Bilingual Proficiency)
  • Kannada (Native / Bilingual Proficiency)
  • Tamil (Elementary Proficiency)

Projects

My Works

  • Lorenz Attractor
    Parallization Algorithm


    C program for visualization of Lorenz Attractor using OpenMP, MPI, CUDA C/C++ and OpenGL for High Performance Computing.

  • Build Passing
    Language C
    Dependencies Latest


  • VLIW
    Simulator


    A Python - Verilog combination that simulates the working of a 32-bit 5-stage pipelined VLIW processor from input assembly code while monitoring the updates in the processor register file.

  • Build Passing
    Language Verilog
    Dependencies Latest


  • Key Distribution Centre
    (Kerberos)


    A multi-threaded GUI application for the client – server communication which uses a Kerberos encryption mechanism for a secure connection.

  • Build Passing
    Language Python
    Dependencies Latest


  • Netlist Viewer
    and Simulator


    A python program that generates a graph from a input verilog .v file, (structural model) or verilog netlist .vm file (Output simulation and Application of TMR approach).

    • Verilog (.v)
    • Verilog Netlist (.vm)
    Build Passing
    Language Python
    Dependencies Latest


  • Sim File
    Generator


    A python program that generates a .sim file from a input boolean expression

  • Build Passing
    Language Python
    Dependencies Latest

Contact

Say Hello

Personal Info

Give me a call


+91 95917 16202

Let's connect

saikaushik609@gmail.com
ssaikaushik0802@gmail.com